Extending battery life is a primary consideration in portable computing devices, such as laptop computers and smartphones. To conserve power, portable computing devices often halt clock signals to specific circuits that become idle during system operation. This clock-stopping technique is effective at reducing power consumption because the Complementary Metal Oxide Semiconductor (CMOS) circuitry within a portable computing device consumes substantially more power while the circuits are switching, and substantially less power while the circuits are idle.
Unfortunately, stopping and starting clock signals in computer systems can adversely affect system performance. For example, a given integrated circuit (IC) within a computer system typically has a power delivery network (PDN), which comprises both on-chip and off-chip components. When a clock signal to the IC (or a clock signal inside the IC) is stopped to save power and is then restarted, the IC immediately starts demanding power from the PDN. Because the PDN has a complex impedance, this sudden increase in demand for power causes a transient voltage response in the PDN. As a result, the voltage supplied to circuits with the IC typically starts to droop and then starts ringing. This fluctuating voltage can cause clock signals and transceivers in the IC to have different delays, which can cause timing margins to decrease and can cause data errors.
These problems with voltage fluctuations can be avoided by simply waiting until the voltage fluctuations diminish which, for example, may involve waiting for tens of nanoseconds. However, in computer systems where clock signals are stopped and started frequently, waiting for these voltage fluctuations to diminish whenever a clock signal is restarted can adversely affect computer system performance.
Hence, what is needed is a method and an apparatus that supports stopping and starting clock signals within a computer system without the above-described voltage fluctuation problems.